Issued Patents
  1. 3-D Stacked Multiprocessor Structures and Methods for Multimodal Operation of Same
    9/13/2016 Issued as US Patent 9,442,884 and 9,471,535 (A. Buyuktosunoglu, P. Emma, M. B. Healy, A. Hartstein, Krishnan Kailas)

  2. Three-Dimensional Processing System Having Independent Calibration and Statistical Collection Layer
    7/12/2016 Issued as US Patent 9,389,876 (P. Emma, A. Hartstein, M. B. Healy, Krishnan Kailas, A. Buyuktosunoglu)

  3. Three-Diimensional Processing System Having at Least One Layer with Circuitry Dedicated to Scan Testing and System State Checkpointing of Other System Layers
    7/5/2016 Issued as US Patent 9,383,411 (A. Buyuktosunoglu, P. Emma, M. B. Healy, A. Hartstein, Krishnan Kailas)

  4. 3-D Stacked Multiprocessor Structure with Vertically Aligned Layout Operating Processors in Independent Mode or in Sharing Mode Running Faster Components
    3/29/2016 Issued as US Patent 9,298,672 (A. Buyuktosunoglu, P. Emma, M. B. Healy, A. Hartstein, Krishnan Kailas)

  5. Three-Dimensional Computer Processor Systems Having Multiple Local Power and Cooling Layers and a Global Interconnection Structure
    11/24/2015 Issued as US Patent 9,195,630 (A. Buyuktosunoglu, P. Emma, M. B. Healy, A. Hartstein, Krishnan Kailas)

  6. Memory Architectures Having Wiring Structures that Enable Different Access Patterns in Multiple Dimensions
    11/17/2015 Issued as US Patent 9,190,118 (A. Buyuktosunoglu, P. Emma, M. B. Healy, A. Hartstein, Krishnan Kailas)

  7. Enhanced Case-splitting based Property Checking
    03/10/2015 Issued as US Patent 8,978,001 and 8,997,030 (Krishnan Kailas, Hari Mony)

  8. 3-D Stacked Multiprocessor Structures and Methods To Enable Reliable Operation Of Processors At Speeds Above Specified Limits
    08/05/2014 Issued as US Patent 8,799,710 and 8,826,073 (A. Buyuktosunoglu, P. Emma, M. B. Healy, A. Hartstein, Krishnan Kailas)

  9. Method and Structure for Provably Fair Random Number Generator
    11/13/2012 Issued as US Patent 8,312,071 and 9,063,807 (Krishnan Kailas, Brian Monwai, Viresh Paruthi)

  10. Method and Apparatus for Fast Synchronization and Out-of-order Execution of Instructions in a Meta-program based Computing System
    10/30/2012 Issued as US Patent 8,301,870 (Krishnan Kailas)

  11. Method and Apparatus for Application-specific Dynamic Cache Placement
    11/16/2010 Issued as US Patent 7,836,256 (Krishnan Kailas, Rajiv Ravindran, Zehra Sura)

  12. Bounded Starvation Checking of an Arbiter Using Formal Verification
    07/06/2010 Issued as US Patent 7,752,369 (Krishnan Kailas, Brian Monwai, Viresh Paruthi)

  13. Method and System for Tracking Instruction Dependency in an Out-of-Order Processor
    05/04/2010 Issued as US Patent 7,711,929 (Bill Burky, Krishnan Kailas)

  14. Method and apparatus for a computing system using meta program representation
    02/16/2010 Issued as US Patent 7,665,070 (Krishnan Kailas)

  15. Method and system for dependency tracking and flush recovery for an out-of-order microprocessor
    02/09/2010 Issued as US Patent 7,660,971 (Vikas Agarwal, Bill Burky, Krishnan Kailas, Balaram Sinharoy)

  16. Method and apparatus for register renaming using multiple physical register files and avoiding associative search
    03/17/2009 Issued as US Patent 7,506,139 (Bill Burky, Krishnan Kailas, Balaram Sinharoy)

  17. Method and apparatus for dynamic priority-based cache replacement
    03/10/2009 Issued as US Patent 7,502,890 (Krishnan Kailas, Rajiv Ravindran, Zehra Sura)

  18. Method and apparatus for providing fast remote register access in a clustered VLIW processor using partitioned register files
    01/27/2009 Issued as US Patent 7,484,075 (Krishnan Kailas)

  19. Computer processing system employing an instruction schedule cache
    01/02/2009 Issued as US Patent 7,454,597 (Krishnan Kailas, Ravi Nair, Sumedh Sathaye, Wolfram Sauer, J-D Wellman)


    Last updated on $Date: 2016/10/30$